1. Field of the Invention
The present invention relates to a microcomputer that can be debugged while it is in practical use.
2. Description of the Prior Art
Referring next to FIG. 14, it illustrates a block diagram showing the structure of a prior art microcomputer as disclosed, as a first conventional example, in Japanese Patent Application Publication (TOKKAIHEI) No. 8-185336, for example. In the figure, reference numeral 1 denotes a user target system, such as a microcomputer-equipped appliance, and numeral 2 denotes a host computer. The user target system 1 includes a serial interface 3 connected to the host computer 2, a memory 4, a monitor program 5 stored in the memory 4, an I/O 6, a microprocessor 7, a register built in the microprocessor 7, and a processor bus 9.
When debugging the user target system 1, the host computer 2 is connected to the serial interface 3. The microcomputer 7 can execute the monitor program 5 to access the memory 4, the I/O 6, and the register 8 by the processor bus 9. The microcomputer 7 can execute and control a user program using a software break instruction and then furnish execution results to the host computer 2 by way of the serial interface 3.
Referring next to FIG. 15, it illustrates a block diagram showing the structure of another prior art microcomputer as disclosed, as a second conventional example, in Japanese Patent Application Publication (TOKKAIHEI) No. 8-185336, for example. In the figure, reference numeral 11 denotes a debugging tool. A microprocessor 7 includes a register 12, a sequencer 13, a bus controller 14, and a transmission path 15. The other structure of the microcomputer of FIG. 15 is the same as that of the microcomputer of FIG. 14.
When debugging the user target system 1, the debugging tool 11 and host computer 2 are connected to the serial interface 3. The debugging tool 11 converts a command from the host computer 2 into an equivalent command intended for debugging, which can be understood by the sequencer 13 of the microprocessor 7. The sequencer 13 of the microprocessor 7 can suspend the execution of a user program according to the command intended for debugging, and access the register 12 by way of the transmission path 15 and the memory 4 or I/O 6 using the bus controller 14. The sequencer 13 of the microprocessor 7 can furnish execution results to the debugging tool 11 by way of the serial interface 3. The debugging tool 11 can convert the execution results into equivalent data which can be understood by the host computer 2 and then furnish the data to the host computer 2.
Referring next to FIG. 16, it illustrates a block diagram showing the structure of another prior art microcomputer as disclosed, as a third conventional example, in Japanese Patent Application Publication (TOKKAIHEI) No. 8-185336, for example. A debugging tool 11 as shown in the figure includes a microprocessor 21 intended for debugging, a monitor program memory 22, and a trace memory 23. The other structure of the microcomputer of FIG. 16 is the same as that of the microcomputer of FIG. 14.
In general, the debugging system as shown in FIG. 16 is called in-circuit emulator. When debugging the user target system 1, the microprocessor 7 is removed from the user target system 1. As an alternative, the microprocessor 7 is disabled. A probe of the debugging tool 11 can be connected to the part of the bus 9 to which the microprocessor 7 was connected, so that the debugging microprocessor 21 can alternatively operate. The debugging microprocessor 21 can execute a monitor program stored in the monitor program memory 22 built in the debugging tool 11 to control execution of a user program or access the memory 4 or I/O 6. The debugging microprocessor 21 can execute a program stored in the memory 4 built in the user target system 1 as if the microprocessor 7 does. The debugging tool 11 includes the trace memory 23 to trace the status of the processor bus of debugging microprocessor 21. The debugging microprocessor 21 can furnish trace information that cannot be obtained from the microprocessor 7. Part of the internal state of the debugging microprocessor 21, which cannot be traced via the processor bus 9, can be traced.
Referring next to FIG. 17, it illustrates a block diagram showing the structure of another prior art microcomputer as disclosed, as a fourth conventional example, in Japanese Patent Application Publication (TOKKAIHEI) No. 8-185336, for example. In the figure, reference numeral 31 denotes a logic analyzer connected to a user target system 1. The other structure of the microcomputer of FIG. 17 is the same as that of the microcomputer of FIG. 14.
In general, the debugging system as shown in FIG. 17 is called pre-processors. When debugging the user target system 1, a probe of the logic analyzer 31 is connected to a processor bus 9 built in the user target system 1, so that accesses to a memory 4 and an I/O 6 by a microprocessor 7 can be traced.
Referring next to FIG. 18, it illustrates a block diagram showing the structure of another prior art microcomputer as disclosed, as an embodiment, in Japanese Patent Application Publication (TOKKAIHEI) No. 8-185336, for example. A debugging tool 11 as shown in the figure includes a monitor program 41. A user target system 1 includes an external debugging interface 42. A microprocessor 7 includes a processor core 43, a debugging module 44, an internal debugging interface 45, and an internal processor bus 46. The other structure of the debugging system of FIG. 18 is the same as that of the debugging system of FIG. 14.
When debugging the user target system 1, the debugging tool 11 is connected to the external debugging interface 42 of the user target system. The processor core 43 can execute the monitor program 41 stored in the debugging tool 11 by way of the internal debugging interface 45 and the debugging module 44. At that time, the processor core 43 furnishes an address and size information to the debugging tool 11. The debugging tool 11 then furnishes a corresponding code of the monitor program 41 to the core processor 43. The monitor program 41 can implement execution control functions, such as reading and writing of a memory 4 or an I/O 6, setting of hardware break points, and specifying of the starting address at which the execution of the user program is to be started. The debugging module 44 can implement a serial monitor bus function, which is enabled in debugging mode, and a PC trace function, a trace trigger function, a hardware break function, a software break function, a debugging interruption function, a debugging reset function, and a mask function, which are enabled in normal mode.
A problem with the prior art debugging system as shown in FIG. 14 is that the monitor program 5 used for debugging a user program has to be pre-stored in the memory 4 of the user target system 1 and this results in upsizing of the memory 4. A further problem is that when the memory 4 storing the user program to be debugged becomes unstable, the monitor program 5 for debugging the user program becomes unstable, too, thus being unable to debug the user program with reliability.
A problem with the prior art debugging system as shown in FIG. 15 is that the transmission path 15 and the bus controller 14 intended for debugging have to be provided in order to access the register 12, and this results in upsizing of the debugging system and hence an increase in the area of the chip.
A problem with the prior art debugging system as shown in FIG. 16 is that since the connection between the user target system 1 and the debugging tool 11 is established by a probe, the connection by the probe easily becomes unstable and the user target system 1 therefore becomes unstable. Another problem is that a variety of probes must be prepared for a variety of types of user target system 1.
The prior art debugging system as shown in FIG. 17 faces the same problems as those that arises in the prior art debugging system as shown in FIG. 16. A further problem with the prior art debugging system of FIG. 17 is that the system does not include any function of controlling execution of the microprocessor 7 and therefore it cannot debug a user program in detail.
A problem with the prior art debugging system as shown in FIG. 18 is that the processor core 43 has to furnish an address and size information to the debugging tool 11 to access the monitor program 41 and the debugging system therefore cannot execute the monitor program 41 at a high speed.
The present invention is proposed to solve the above problems. It is therefore an object of the present invention to provide a microcomputer capable of reducing the size of a debugging system required for debugging the microcomputer including a user program to be executed by the microcomputer and allowing the debugging system to debug the microcomputer with reliability and with efficiency by enabling a CPU built in the microcomputer to execute a debugging program supplied from a debugging tool disposed outside the microcomputer.
In accordance with one aspect of the present invention, there is provided a microcomputer comprising: a serial interface for receiving a debugging program applied thereto from a debugging tool; a first register for holding an instruction code included with the debugging program, which is applied to the microcomputer via the serial interface; and a central processing unit or CPU for executing the instruction code held by the first register.
Preferably, the microcomputer can further comprise a buffer for holding one or more instruction codes supplied thereto from the first register. The CPU can execute each of the plurality of instruction codes held by the buffer. Preferably, the serial interface is a JTAT (Joint Test Action Group) interface.
The buffer can include a plurality of storage areas for storing a plurality of instruction codes sequentially furnished thereto from the first register, and the first register holds an entry specifying code specifying in which area of the buffer a next instruction code from the first register, which is included with the debugging program and is applied to the microcomputer via the serial interface, is to be stored, as well as the instruction code. Further, the microcomputer can further comprise an input control unit for furnishing the instruction code held by the first register to a storage area of the buffer specified by the entry specifying code to allow the storage area to hold the instruction code. As an alternative, the buffer includes a plurality of storage areas for storing a plurality of instruction codes sequentially furnished thereto from the first register, and the microcomputer further comprises an input control unit for, when the microcomputer sequentially receives a plurality of instruction codes from the debugging tool, sequentially furnishing the plurality of instruction codes sequentially held by the first register to the respective storage areas of the buffer, to allow the plurality of storage areas to hold the plurality of instruction codes, respectively.
In accordance with a preferred embodiment, the microcomputer further comprises a valid control unit for generating a valid signal indicating whether the instruction code held by the first register is valid or invalid, and a second register for holding the value of the valid signal generated by the valid control unit, for enabling the debugging tool to read the value of the valid signal byway of the serial interface.
In accordance with another preferred embodiment, the microcomputer further comprises a valid control unit for generating a valid signal indicating whether the instruction code held by the first register is valid or invalid, and an internal bus interface unit for furnishing a negated access completion signal to the CPU when the valid signal generated by the valid control unit indicates that the instruction code held by the first register is invalid, and for furnishing an asserted access completion signal to the CPU when the valid signal generated by the valid control unit indicates that the instruction code held by the first register is valid.
In accordance with another preferred embodiment, the microcomputer further comprises a valid control unit for generating a valid signal indicating whether the instruction code held by the first register is valid or invalid, and an output control unit, responsive to an instruction-fetching request from the CPU, for furnishing a branch instruction to prevent a program counter""s current value from incrementing to the CPU when the valid signal generated by the valid control unit indicates that the instruction code held by the first register is invalid. The output control unit can furnish the branch instruction to prevent the program counter""s current value from incrementing to the CPU when the instruction-fetching request is an instruction-prefetching request or when the valid signal generated by the valid control unit indicates that the instruction code held by the first register is invalid.
In accordance with another preferred embodiment, the microcomputer further comprises a second register for holding the value of an instruction code setting completion signal applied thereto by way of the serial interface, indicating that one or more instruction codes have already been set to the buffer; an instruction code setting completion detecting unit for determining whether or not the second register is holding the value of the instruction code setting completion signal; and a valid control unit for generating a valid signal indicating that one or more instruction codes held by the buffer are valid when the instruction code setting completion signal unit detects the holding of the value of the instruction code setting completion signal.
In accordance with another preferred embodiment, the microcomputer further comprises a third register into which the CPU can write data, for enabling the debugging tool to read the data by way of the serial interface. The microcomputer can further comprise a valid control unit for generating a valid signal indicating whether data held by the third register is valid or invalid, and a second register for holding the value of the valid signal generated by the valid control unit and for enabling the debugging tool to read the value of the valid signal by way of the serial interface.
In accordance with another preferred embodiment, the microcomputer further comprises a fourth register for holding data applied thereto by way of the serial interface. The CPU can read the data held by the fourth register. The microcomputer can further comprise a valid control unit for generating a valid signal indicating whether data held by the fourth register is valid or invalid, and a second register for holding the value of the valid signal generated by the valid control unit and for enabling the debugging tool to read the value of the valid signal by way of the serial interface.
Preferably, the serial interface and the first register operate on a first clock, and the buffer and the CPU operate on a second clock independent of the first clock.
In accordance with a preferred embodiment of the present invention, the microcomputer further comprises: a second register that operates on the first clock, for holding the value of a signal indicating whether an instruction code can be set to the first register and for enabling the debugging tool to read the value of the signal by way of the serial interface; an access detecting unit that operates on the first clock, for generating an access detection signal when detecting an access from the debugging tool to the first register; an access detection signal transmitting unit that operates on the second clock, for generating an access detection recognition signal in response to the access detection signal from the access detecting unit; a valid control unit that operates on the second clock, for generating a valid signal indicating that one or more instruction codes held by the buffer are valid or invalid; and a second-register control unit that operates on the first clock, for causing the second register to hold a value indicating that any instruction code cannot be set to the first register in response to the access detection signal from the access detecting unit, and for causing the second register to hold the value of the valid signal generated by the valid control unit in response to the access detection recognition signal from the access detection signal transmitting unit.
In accordance with another preferred embodiment of the present invention, the microcomputer further comprises: a second register that operates on the first clock, for holding the value of a signal indicating whether one or more instruction codes have already been set to the buffer; an instruction code setting completion detecting unit that operates on the first clock, for generating an instruction code setting completion signal when determining that the second register is holding the value of the signal; an instruction code setting completion signal transmitting unit that operates on the second clock, for generating an instruction code setting completion recognition signal in response to the instruction code setting completion signal from the instruction code setting completion signal unit; a valid control unit that operates on the second clock, for generating a valid signal indicating that the one or more instruction codes held by the buffer are valid or invalid; and a second-register control unit that operates on the first clock, for causing the second register to hold a value indicating that one or more instruction codes have already been set to the buffer in response to the instruction code setting completion signal from the instruction code setting completion generating unit, and for causing the second register to hold the value of the valid signal generated by the valid control unit in response to the instruction code setting completion recognition signal from the instruction code setting completion signal transmitting unit.
In accordance with another preferred embodiment of the present invention, the microcomputer further comprises: a second register that operates on the first clock, for holding the value of a signal indicating whether data held by a third register is valid or invalid, and for enabling the debugging tool to read the value of the signal by way of the serial interface; an access detecting unit that operates on the first clock, for generating an access detection signal when detecting an access from the debugging tool to the third register; an access detection signal transmitting unit that operates on the second clock, for generating an access detection recognition signal in response to the access detection signal from the access detecting unit; a valid control unit that operates on the second clock, for generating a valid signal indicating that data held by a fifth register is valid or invalid; and a second-register control unit that operates on the first clock, for causing the second register to hold a value indicating that the data held by the third register is invalid in response to the access detection signal from the access detecting unit, and for causing the second register to hold the value of the valid signal generated by the valid control unit in response to the access detection recognition signal from the access detection signal transmitting unit.
In accordance with another preferred embodiment of the present invention, the microcomputer further comprises: a second register that operates on the first clock, for holding the value of a signal indicating whether data held by a fourth register has already been read by the CPU, and for enabling the debugging tool to read the value of the signal by way of the serial interface; an access detecting unit that operates on the first clock, for generating an access detection signal when detecting an access from the debugging tool to the fourth register; an access detection signal transmitting unit that operates on the second clock, for generating an access detection recognition signal in response to the access detection signal from the access detecting unit; a valid control unit that operates on the second clock, for generating a valid signal indicating whether data that has been transferred from the fourth register and is held by a sixth register is valid or invalid; and a second-register control unit that operates on the first clock, for causing the second register to hold a value indicating that the data held by the fourth register has not been read yet by the CPU in response to the access detection signal from the access detecting unit, and for causing the second register to hold the value of the valid signal generated by the valid control unit in response to the access detection recognition signal from the access detection signal transmitting unit.